MC9S08RG60 Datasheet, PDF (219/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
SS⁽¹⁾
(OUTPUT)
SPSCK
(CPOL = 0)
(OUTPUT)
SPSCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN⁽²⁾
12
11
BIT 6 . . . 1
9
MOSI
(OUTPUT) ^{PORT DATA}
MASTER MSB OUT⁽²⁾
10
BIT 6 . . . 1
11
3
12
LSB IN
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure C-12 SPI Master Timing (CPHA =1)
SS
(INPUT)
SPSCK
(CPOL = 0)
(INPUT)
SPSCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
1
12
2
4
4
11
7
SLAVE MSB OUT
5
6
MSB IN
9
BIT 6 . . . 1
BIT 6 . . . 1
11 3
12
8
10
10
SLAVE LSB OUT
SEE
NOTE
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure C-13 SPI Slave Timing (CPHA = 0)
Freescale Semiconductor
MC9S08RC/RD/RE/RG
219