MC9S08RG60 Datasheet, PDF (138/232 Pages) Motorola, Inc – Microcontrollers

Timer/PWM (TPM) Module
Table 10-1 TPM Clock Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
0:0
No clock selected (TPM disabled)
0:1
Bus rate clock (BUSCLK)
1:0
Fixed system clock (XCLK)
1:1
External source (TPM1 Ext Clk)¹²
1 _{The maximum frequency that is allowed as an external clock is one-fourth of the bus}
frequency.
2 _{When the TPM1CH0 pin is selected as the TPM clock source, the corresponding}
ELS0B:ELS0A control bits should be set to 0:0 so channel 0 does not try to use the same pin
for a conflicting function.
PS2:PS1:PS0 — Prescale Divisor Select
This 3-bit field selects one of eight divisors for the TPM clock input as shown in Table 10-2. This
prescaler is located after any clock source synchronization or clock source selection, so it affects
whatever clock source is selected to drive the TPM system.
Table 10-2 Prescale Divisor Selection
PS2:PS1:PS0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
TPM Clock Source Divided-By
1
2
4
8
16
32
64
128
10.7.2 Timer x Counter Registers (TPM1CNTH:TPM1CNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPM1CNTH or
TPM1CNTL, or any write to the timer status/control register (TPM1SC).
Reset clears the TPM counter registers.
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MC9S08RC/RD/RE/RG
Freescale Semiconductor