MC9S08RG60 Datasheet, PDF (217/232 Pages) Motorola, Inc – Microcontrollers

TPM1CHn
t_ICPW
SoC Guide — MC9S08RG60/D Rev 1.10
TPM1CHn
t_ICPW
Figure C-10 Timer Input Capture Pulse
C.9.3 SPI Timing
Table C-11 and Figure C-11 through Figure C-14 describe the timing requirements for the SPI system.
Table C-11 SPI Timing
No.
Function
Operating frequency
Master
Slave
SPSCK period
1
Master
Slave
Enable lead time
2
Master
Slave
Enable lag time
3
Master
Slave
Clock (SPSCK) high or low time
4
Master
Slave
Data setup time (inputs)
5
Master
Slave
Data hold time (inputs)
6
Master
Slave
7 Slave access time
8 Slave MISO disable time
Data valid (after SPSCK edge)
9
Master
Slave
Symbol
f_op
t_SPSCK
t_Lead
t_Lag
t_WSPSCK
t_SU
t_HI
t_a
t_dis
t_v
Min
Max
f_Bus/2048
dc
2
4
f_Bus/2
f_Bus/4
2048
—
1/2
—
1
—
1/2
—
1
—
t_cyc – 30
t_cyc – 30
15
15
1024 t_cyc
—
—
—
0
—
25
—
—
1
—
1
—
25
—
25
Unit
Hz
t_cyc
t_cyc
t_SPSCK
t_cyc
t_SPSCK
t_cyc
ns
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
Freescale Semiconductor
MC9S08RC/RD/RE/RG
217