MC9S08RG60 Datasheet, PDF (174/232 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
SPR2:SPR1:SPR0 — SPI Baud Rate Divisor
This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in Table 12-3. The
input to this divider comes from the SPI baud rate prescaler (see Figure 12-4). The output of this
divider is the SPI bit rate clock for master mode.
Table 12-3 SPI Baud Rate Divisor
SPR2:SPR1:SPR0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Rate Divisor
2
4
8
16
32
64
128
256
12.4.4 SPI Status Register (SPI1S)
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0s.
Writes have no meaning or effect.
Bit 7
6
5
4
3
2
1
Bit 0
Read: SPRF
0
SPTEF MODF
0
0
0
0
Write:
Reset: 0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-10 SPI Status Register (SPI1S)
SPRF — SPI Read Buffer Full Flag
SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI
data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the SPI data
register.
1 = Data available in the receive data buffer.
0 = No data available in the receive data buffer.
174
MC9S08RC/RD/RE/RG
Freescale Semiconductor