MC9S08RG60 Datasheet, PDF (72/232 Pages) Motorola, Inc – Microcontrollers

Resets, Interrupts, and System Configuration
5.8.8 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVWF
0
0
Write:
LVWACK
0
PPDF
0
PDC PPDC
PPDACK
Reset: 0⁽¹⁾
0
0
0
0
0
0
0
= Unimplemented or Reserved
U = Unaffected by reset
NOTES:
1. LVWF will be set in the case when V_Supply transitions below the trip point or after reset and V_Supply is already
below V_LVW.
Figure 5-9 System Power Management Status and Control 2 Register (SPMSC2)
LVWF — Low-Voltage Warning Flag
The LVWF bit indicates the low voltage warning status.
1 = Low voltage warning is present or was present.
0 = Low voltage warning not present.
LVWACK — Low-Voltage Warning Acknowledge
The LVWF bit indicates the low voltage warning status.
Writing a logic 1 to LVWACK clears LVWF to a logic 0 if a low voltage warning is not present.
PPDF — Partial Power Down Flag
The PPDF bit indicates that the MCU has exited the stop2 mode.
1 = Stop2 mode recovery.
0 = Not stop2 mode recovery.
PPDACK — Partial Power Down Acknowledge
Writing a logic 1 to PPDACK clears the PPDF bit.
PDC — Power Down Control
The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
1 = Power down modes are enabled.
0 = Power down modes are disabled.
PPDC — Partial Power Down Control
The write-once PPDC bit controls which power down mode, stop1 or stop2, is selected.
1 = Stop2, partial power down, mode enabled if PDC set.
0 = Stop1, full power down, mode enabled if PDC set.
72
MC9S08RC/RD/RE/RG
Freescale Semiconductor