MC9S08RG60 Datasheet, PDF (67/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
Illegal address areas only exist in the 16K and 8K versions and are defined as:
• $0440–$17FF — Gap from end of RAM to start of high-page registers
• $1834–$BFFF — Gap from end of high-page registers to start of FLASH memory
Unused and reserved locations in register areas are not considered designated illegal addresses and do
not trigger illegal address resets.
LVD — Low Voltage Detect
If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This
bit is also set by POR.
1 = Reset caused by LVD trip or POR
0 = Reset not caused by LVD trip or POR
5.8.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return $00.
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
0
Write:
BDFR⁽¹⁾
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
NOTES:
1. BDFR is writable only through serial background debug commands, not from user programs.
Figure 5-4 System Background Debug Force Reset Register (SBDFR)
BDFR — Background Debug Force Reset
A serial background command such as WRITE_BYTE may be used to allow an external debug host
to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This bit cannot be written
from a user program.
5.8.4 System Options Register (SOPT)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
must be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
Freescale Semiconductor
MC9S08RC/RD/RE/RG
67