MC9S08RG60 Datasheet, PDF (43/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f_FCLK). The time for one cycle of FCLK is t_FCLK = 1/f_FCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where t_FCLK = 5 µs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5 Program and Erase Times
Parameter
Cycles of FCLK
Byte program
9
Byte program (burst)
4
Page erase
4000
Mass erase
NOTES:
1. Excluding start/end overhead
20,000
Time if FCLK = 200 kHz
45 µs
20 µs⁽¹⁾
20 ms
100 ms
4.4.3 Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this
write is latched into the FLASH interface. This write is a required first step in any command
sequence. For erase and blank check commands, the value of the data is not important. For page
erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For
mass erase and blank check commands, the address can be any address in the FLASH memory.
Whole pages of 512 bytes are the smallest block of FLASH that may be erased. In the 60K version,
there are two instances where the size of a block that is accessible to the user is less than 512 bytes:
the first page following RAM, and the first page following the high page registers. These pages are
overlapped by the RAM and high page registers respectively.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check ($05), byte program ($20), burst program ($25), page erase ($40), and mass erase ($41). The
command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Aborting a command in this way sets the FACCERR access error flag, which must be cleared before
starting a new command.
Freescale Semiconductor
MC9S08RC/RD/RE/RG
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