MC9S08RG60 Datasheet, PDF (173/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
12.4.3 SPI Baud Rate Register (SPI1BR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Bit 7
6
5
4
3
Read: 0
0
SPPR2 SPPR1 SPPR0
Write:
Reset: 0
0
0
0
0
= Unimplemented or Reserved
2
1
Bit 0
SPR2 SPR1 SPR0
0
0
0
Figure 12-9 SPI Baud Rate Register (SPI1BR)
SPPR2:SPPR1:SPPR0 — SPI Baud Rate Prescale Divisor
This 3-bit field selects one of eight divisors for the SPI baud rate prescaler as shown in Table 12-2. The
input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of
the SPI baud rate divider (see Figure 12-4).
Table 12-2 SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Prescaler Divisor
1
2
3
4
5
6
7
8
Freescale Semiconductor
MC9S08RC/RD/RE/RG
173