MC9S08RG60 Datasheet, PDF (203/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
14.5.3.8 Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
Bit 7
6
5
4
Read:
0
0
TRGSEL BEGIN
Write:
Reset: 0
0
0
0
= Unimplemented or Reserved
3
2
TRG3 TRG2
0
0
Figure 14-8 Debug Trigger Register (DBGT)
1
TRG1
0
Bit 0
TRG0
0
TRGSEL — Trigger Type
Controls whether the match outputs from comparators A and B are qualified with the opcode tracking
logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode
at the match address is actually executed.
1 = Trigger if opcode at compare address is executed (tag).
0 = Trigger on access to compare address (force).
BEGIN — Begin/End Trigger Select
Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the
capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed
to be begin traces.
1 = Trigger initiates data storage (begin trace).
0 = Data stored in FIFO until trigger (end trace).
TRG3:TRG2:TRG1:TRG0 — Select Trigger Mode
Selects one of nine triggering modes
Freescale Semiconductor
MC9S08RC/RD/RE/RG
203