MC9S08RG60 Datasheet, PDF (64/232 Pages) Motorola, Inc – Microcontrollers

Resets, Interrupts, and System Configuration
5.7 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) function can be used to generate periodic interrupts based on a divide of the
external oscillator or an internal 1-kHz clock source. It can also be used to wake the MCU from stop2 or
stop3 mode when using the internal 1-kHz clock source.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to disable the clock source to the real-time interrupt or select one of
seven wakeup delays between 8 ms and 1.024 seconds. The 1-kHz clock source and therefore the periodic
rates have a tolerance of about ±30 percent. The RTI has a local interrupt enable, RTIE, to allow masking
of the real-time interrupt. It can be disabled by writing 0:0:0 to RTIS2:RTIS1:RTIS0 so the clock source
is disabled and no interrupts will be generated. See 5.8.6 System Real-Time Interrupt Status and Control
Register (SRTISC) for detailed information about this register.
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and five 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in the Memory section of this data sheet for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in Modes
of Operation.
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes two unimplemented bits that always read 0, four read/write bits, one
read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status,
and acknowledge IRQ events.
Bit 7
6
5
4
Read: 0
Write:
0
IRQEDG IRQPE
Reset: 0
0
0
0
= Unimplemented or Reserved
3
2
1
Bit 0
IRQF
0
IRQIE IRQMOD
IRQACK
0
0
0
0
Figure 5-2 Interrupt Request Status and Control Register (IRQSC)
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MC9S08RC/RD/RE/RG
Freescale Semiconductor