MC9S08RG60 Datasheet, PDF (68/232 Pages) Motorola, Inc – Microcontrollers

Resets, Interrupts, and System Configuration
Bit 7
6
5
4
3
2
Read:
COPE
Write:
COPT STOPE
0
0
Reset: 1
1
0
1
0
0
= Unimplemented or Reserved
Figure 5-5 System Options Register (SOPT)
1
Bit 0
BKGDPE RSTPE
1
1
COPE — COP Watchdog Enable
This write-once bit defaults to 1 after reset.
1 = COP watchdog timer enabled (force reset on timeout).
0 = COP watchdog timer disabled.
COPT — COP Watchdog Timeout
This write-once bit defaults to 1 after reset.
1 = Long timeout period selected (2²⁰ cycles of BUSCLK).
0 = Short timeout period selected (2¹⁸ cycles of BUSCLK).
STOPE — Stop Mode Enable
This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a
user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
1 = Stop mode enabled.
0 = Stop mode disabled.
BKGDPE — Background Debug Mode Pin Enable
The BKGDPE bit enables the PTD0/BKGD/MS pin to function as BKGD/MS. When the bit is clear,
the pin will function as PTD0, which is an output only general purpose I/O. This pin always defaults
to BKGD/MS function after any reset.
1 = BKGD pin enabled.
0 = BKGD pin disabled.
RSTPE — RESET Pin Enable
The RSTPE bit enables the PTD1/RESET pin to function as RESET. When the bit is clear, the pin will
function as PTD1, which is an output only general purpose I/O. This pin always defaults to RESET
function after any reset.
1 = RESET pin enabled
0 = RESET pin disabled
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MC9S08RC/RD/RE/RG
Freescale Semiconductor