MC9S08RG60 Datasheet, PDF (108/232 Pages) Motorola, Inc – Microcontrollers

Carrier Modulator Transmitter (CMT) Module
CMTDIV1:CMTDIV0 — CMT Clock Divide Prescaler
The CMT clock divide prescaler causes the CMT to be clocked at the BUS CLOCK frequency, or the
BUS CLOCK frequency divided by 1, 2, 4, or 8. Because these bits are not double buffered, they
should not be changed during a transmission.
Table 7-3 CMT Clock Divide Prescaler
CMTDIV1:CMTDIV0
00
01
10
11
CMT Clock Divide
BUS CLOCK ÷ 1
BUS CLOCK ÷ 2
BUS CLOCK ÷ 4
BUS CLOCK ÷ 8
EXSPC — Extended Space Enable
The EXSPC bit enables extended space operation.
1 = Extended space enabled
0 = Extended space disabled
BASE — Baseband Enable
When set, the BASE bit disables the carrier generator and forces the carrier output high for generation
of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output
toggles at the frequency determined by values stored in the carrier data registers. See 7.5.2.2 Baseband
Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during
a transmission.
1 = Baseband mode enabled
0 = Baseband mode disabled
FSK — FSK Mode Select
The FSK bit enables FSK operation.
1 = CMT operates in FSK mode
0 = CMT operates in time or baseband mode
EOCIE — End of Cycle Interrupt Enable
A CPU interrupt will be requested when EOCF is set if EOCIE is high.
1 = CPU interrupt enabled
0 = CPU interrupt disabled
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MC9S08RC/RD/RE/RG
Freescale Semiconductor