MC9S08RG60 Datasheet, PDF (86/232 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Source
Form
Table 6-1 HCS08 Instruction Set Summary (Sheet 2 of 6)
Operation
Description
Effect
on CCR
VH I NZC
BHCS rel
Branch if Half Carry Bit
Set
Branch if (H) = 1
– – – – – – REL
29 rr
3
BHI rel
Branch if Higher
Branch if (C) | (Z) = 0
– – – – – – REL
22 rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
Branch if (C) = 0
– – – – – – REL
24 rr
3
BIH rel
Branch if IRQ Pin High
Branch if IRQ pin = 1
– – – – – – REL
2F rr
3
BIL rel
Branch if IRQ Pin Low
Branch if IRQ pin = 0
– – – – – – REL
2E rr
3
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test
(A) & (M)
(CCR Updated but Operands
Not Changed)
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
A5 ii
2
B5 dd
3
C5 hh ll 4
D5 ee ff 4
E5 ff
3
F5
3
9ED5 ee ff 5
9EE5 ff
4
BLE rel
Branch if Less Than
or Equal To
(Signed Operands)
Branch if (Z) | (N ⊕ V) = 1
– – – – – – REL
93 rr
3
BLO rel
Branch if Lower
(Same as BCS)
Branch if (C) = 1
– – – – – – REL
25 rr
3
BLS rel
Branch if Lower or Same
Branch if (C) | (Z) = 1
– – – – – – REL
23 rr
3
BLT rel
Branch if Less Than
(Signed Operands)
Branch if (N ⊕ V ) = 1
– – – – – – REL
91 rr
3
BMC rel
Branch if Interrupt Mask
Clear
Branch if (I) = 0
– – – – – – REL
2C rr
3
BMI rel
Branch if Minus
Branch if (N) = 1
– – – – – – REL
2B rr
3
BMS rel
Branch if Interrupt Mask
Set
Branch if (I) = 1
– – – – – – REL
2D rr
3
BNE rel
Branch if Not Equal
Branch if (Z) = 0
– – – – – – REL
26 rr
3
BPL rel
Branch if Plus
Branch if (N) = 0
– – – – – – REL
2A rr
3
BRA rel
Branch Always
No Test
– – – – – – REL
20 rr
3
BRCLR n,opr8a,rel
Branch if Bit n in Memory
Clear
Branch if (Mn) = 0
–––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01 dd rr 5
03 dd rr 5
05 dd rr 5
07 dd rr 5
09 dd rr 5
0B dd rr 5
0D dd rr 5
0F dd rr 5
BRN rel
Branch Never
Uses 3 Bus Cycles
– – – – – – REL
21 rr
3
BRSET n,opr8a,rel
Branch if Bit n in Memory
Set
Branch if (Mn) = 1
–––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00 dd rr 5
02 dd rr 5
04 dd rr 5
06 dd rr 5
08 dd rr 5
0A dd rr 5
0C dd rr 5
0E dd rr 5
BSET n,opr8a
Set Bit n in Memory
Mn ← 1
DIR (b0)
10 dd
5
DIR (b1)
12 dd
5
DIR (b2)
14 dd
5
–
–
–
–
–
–
DIR (b3)
DIR (b4)
16 dd
18 dd
5
5
DIR (b5)
1A dd
5
DIR (b6)
1C dd
5
DIR (b7)
1E dd
5
BSR rel
Branch to Subroutine
PC ← (PC) + $0002
push (PCL); SP ← (SP) – $0001
push (PCH); SP ← (SP) – $0001
PC ← (PC) + rel
– – – – – – REL
AD rr
5
86
MC9S08RC/RD/RE/RG
Freescale Semiconductor