MC9S08RG60 Datasheet, PDF (88/232 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Source
Form
Table 6-1 HCS08 Instruction Set Summary (Sheet 4 of 6)
Operation
Description
Effect
on CCR
VH I NZC
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR
Memory with
Accumulator
A ← (A ⊕ M)
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
A8 ii
2
B8 dd
3
C8 hh ll 4
D8 ee ff 4
E8 ff
3
F8
3
9ED8 ee ff 5
9EE8 ff
4
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M ← (M) + $01
A ← (A) + $01
X ← (X) + $01
M ← (M) + $01
M ← (M) + $01
M ← (M) + $01
––
DIR
INH
–
INH
IX1
IX
SP1
3C dd
5
4C
1
5C
1
6C ff
5
7C
4
9E6C ff
6
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump
PC ← Jump Address
DIR
EXT
– – – – – – IX2
IX1
IX
BC dd
3
CC hh ll 4
DC ee ff 4
EC ff
3
FC
3
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – $0001
Push (PCH); SP ← (SP) – $0001
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD dd
5
CD hh ll 6
DD ee ff 6
ED ff
5
FD
5
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory
A ← (M)
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
A6 ii
2
B6 dd
3
C6 hh ll 4
D6 ee ff 4
E6 ff
3
F6
3
9ED6 ee ff 5
9EE6 ff
4
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Load Index Register (H:X)
from Memory
H:X ← (M:M + $0001)
0––
IMM
DIR
EXT
– IX
IX2
IX1
SP1
45 jj kk 3
55 dd
4
32 hh ll 5
9EAE
5
9EBE ee ff 6
9ECE ff
5
9EFE ff
5
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory
X ← (M)
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
AE ii
2
BE dd
3
CE hh ll 4
DE ee ff 4
EE ff
3
FE
3
9EDE ee ff 5
9EEE ff
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
C
b7
0
b0
––
DIR
38 dd
5
INH
48
1
INH
58
1
IX1
68 ff
5
IX
78
4
SP1
9E68 ff
6
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right
0
b7
C
b0
DIR
34 dd
5
INH
44
1
––0
INH
IX1
54
1
64 ff
5
IX
74
4
SP1
9E64 ff
6
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)_destination ← (M)_source
H:X ← (H:X) + $0001 in
IX+/DIR and DIR/IX+ Modes
0––
DIR/DIR
–
DIR/IX+
IMM/DIR
IX+/DIR
4E dd dd 5
5E dd
5
6E ii dd 4
7E dd
5
MUL
Unsigned multiply
X:A ← (X) × (A)
– 0 – – – 0 INH
42
5
88
MC9S08RC/RD/RE/RG
Freescale Semiconductor