MC9S08RG60 Datasheet, PDF (42/232 Pages) Motorola, Inc – Microcontrollers

Memory
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See 4.5 Security for a detailed description of
the security feature.
4.4 FLASH
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire background debug interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
4.4.1 Features
Features of the FLASH memory include:
• FLASH Size
– MC9S08RC/RD/RE/RG60 — 63374 bytes (124 pages of 512 bytes each)
– MC9S08RC/RD/RE/RG32 — 32768 bytes (64 pages of 512 bytes each)
– MC9S08RC/RD/RE16 — 16384 bytes (32 pages of 512 bytes each)
– MC9S08RC/RD/RE8 — 8192 bytes (16 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for FLASH and RAM
• Auto power-down for low-frequency read accesses
4.4.2 Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f_FCLK) between 150 kHz and
200 kHz (see 4.6.1 FLASH Clock Divider Register (FCDIV)). This register can be written only once, so
normally this write is done during reset initialization. FCDIV cannot be written if the access error flag,
FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV
register. One period of the resulting clock (1/f_FCLK) is used by the command processor to time program
and erase pulses. An integer number of these timing pulses are used by the command processor to complete
a program or erase command.
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MC9S08RC/RD/RE/RG
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