MC9S08RG60 Datasheet, PDF (57/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
Chapter 5 Resets, Interrupts, and System Configuration
5.1 Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08RC/RD/RE/RG. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this data sheet. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems having their own sections but are part of the system control logic.
5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation:
– Power-on detection (POR)
– Low voltage detection (LVD) with enable
– External reset pin with enable (RESET)
– COP watchdog with enable and two timeout choices
– Illegal opcode
– Illegal address (on 16K and 8K devices)
– Serial command from a background debug host
• Reset status register (SRS) to indicate source of most recent reset; flag to indicate stop2 (partial
power down) mode recovery (PPDF)
• Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)
Freescale Semiconductor
MC9S08RC/RD/RE/RG
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