MC9S08RG60 Datasheet, PDF (155/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
PT — Parity Type
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number
of 1s in the data character, including the parity bit, is even.
1 = Odd parity.
0 = Even parity.
11.9.3 SCI Control Register 2 (SCI1C2)
This register can be read or written at any time.
Bit 7
6
5
4
3
Read:
TIE
TCIE
RIE
ILIE
TE
Write:
Reset: 0
0
0
0
0
2
1
Bit 0
RE
RWU SBK
0
0
0
Figure 11-8 SCI Control Register 2 (SCI1C2)
TIE — Transmit Interrupt Enable (for TDRE)
1 = Hardware interrupt requested when TDRE flag is 1.
0 = Hardware interrupts from TDRE disabled (use polling).
TCIE — Transmission Complete Interrupt Enable (for TC)
1 = Hardware interrupt requested when TC flag is 1.
0 = Hardware interrupts from TC disabled (use polling).
RIE — Receiver Interrupt Enable (for RDRF)
1 = Hardware interrupt requested when RDRF flag is 1.
0 = Hardware interrupts from RDRF disabled (use polling).
ILIE — Idle Line Interrupt Enable (for IDLE)
1 = Hardware interrupt requested when IDLE flag is 1.
0 = Hardware interrupts from IDLE disabled (use polling).
TE — Transmitter Enable
1 = Transmitter on.
0 = Transmitter off.
TE must be 1 in order to use the SCI transmitter. Normally, when TE = 1, the SCI forces the TxD1 pin
to act as an output for the SCI system. If LOOPS = 1 and RSRC = 0, the TxD1 pin reverts to being a
port B general-purpose I/O pin even if TE = 1.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the
direction of traffic on the single SCI communication line (TxD1 pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is
in progress. Refer to 11.4.2 Send Break and Queued Idle for more details.
Freescale Semiconductor
MC9S08RC/RD/RE/RG
155