PIC18F258 Datasheet, PDF (97/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

9.2 PORTB, TRISB and LATB Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= ‘0’)
will make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATB register,
read and write the latched output value for PORTB.
EXAMPLE 9-2:
CLRF PORTB
CLRF LATB
MOVLW 0CFh
MOVWF TRISB
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
FIGURE 9-4:
RB7:RB4 PINS BLOCK
DIAGRAM
RBPU⁽²⁾
Data Bus
WR LATB
or
WR PORTB
Data Latch
DQ
CK
TRIS Latch
DQ
VDD
P
Weak
Pull-up
I/O pin⁽¹⁾
WR TRISB
CK
RD TRISB
TTL
Input
Buffer
ST
Buffer
RD LATB
RD PORTB
Set RBIF
Latch
QD
EN
Q1
From other
RB7:RB4 pins
QD
EN
Q3
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
PIC18FXX8
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON register).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 9-5:
RBPU⁽²⁾
Data Bus
WR Port
WR TRIS
RB1:RB0 PINS BLOCK
DIAGRAM
Data Latch
DQ
CK
VDD
P
Weak
Pull-up
I/O pin⁽¹⁾
TRIS Latch
DQ
CK
TTL
Input
Buffer
RD TRIS
QD
EN
RD Port
RBx/INTx
Schmitt Trigger
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 95