PIC18F258 Datasheet, PDF (263/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
24.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18FXX8 devices have a Watchdog Timer, which
is permanently enabled via the configuration bits or
software controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer neces-
sary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
24.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using Table Reads and
Table Writes.
Programming the configuration registers is done in a
manner similar to programming the FLASH memory.
The EECON1 register WR bit starts a self-timed write
to the configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointed to the
configuration register sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWT instruction can
write a ‘1’ or a ‘0’ into the cell.
TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300001h CONFIG1H
—
—
OSCSEN
—
—
FOSC2 FOSC1 FOSC0
300002h CONFIG2L
—
—
—
—
BORV1 BORV0 BOREN
300003h CONFIG2H
—
—
—
—
WDTPS2 WDTPS1 WDTPS0
300006h CONFIG4L DEBUG
—
—
—
—
LVP
—
300008h CONFIG5L
—
—
—
—
CP3
CP2
CP1
300009h CONFIG5H CPD
CPB
—
—
—
—
—
30000Ah CONFIG6L
—
—
—
—
WRT3
WRT2
WRT1
30000Bh CONFIG6H WRTD WRTB WRTC
—
—
—
—
30000Ch CONFIG7L
—
—
—
—
EBTR3 EBTR2 EBTR1
30000Dh CONFIG7H
—
EBTRB
—
—
—
—
—
3FFFFEh DEVID1
DEV2 DEV1
DEV0
REV4
REV3
REV2
REV1
3FFFFFh DEVID2
DEV10 DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 24-11 for DEVID1 values.
PWRTEN
WDTEN
STVREN
CP0
—
WRT0
—
EBTR0
—
REV0
DEV3
--1- -111
---- 1111
---- 1111
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
(1)
0000 1000
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 261