PIC18F258 Datasheet, PDF (355/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
FIGURE 27-22: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK ¹³²
A/D DATA
9
8 7 ^{... ...} 2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
TCY
GO
DONE
SAMPLE
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 27-24: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D clock period
PIC18FXX8
1.6
20⁽⁵⁾ µs TOSC based, VREF ≥ 3.0V
PIC18LFXX8
3.0
20⁽⁵⁾ µs TOSC based, VREF full range
PIC18FXX8
2.0
6.0 µs A/D RC mode
PIC18LFXX8
3.0
9.0 µs A/D RC mode
131 TCNV Conversion time
(not including acquisition time) (Note 1)
11
12
TAD
132 TACQ Acquisition time (Note 3)
15
—
µs -40°C ≤ Temp ≤ +125°C
10
—
µs 0°C ≤ Temp ≤ +125°C
135 TSWC Switching time from convert → sample
— (Note 4)
136 TAMP Amplifier settling time (Note 2)
1
—
µs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 20.0 for minimum conditions when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels
is 50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 353