PIC18F258 Datasheet, PDF (225/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

19.3.5 LOOPBACK MODE
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers, without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself, just as if they
were coming from another node. The Loopback mode
is a silent mode, meaning no messages will be trans-
mitted while in this state, including error flags or
Acknowledge signals. The TXCAN pin will revert to port
I/O while the device is in this mode. The filters and
masks can be used to allow only particular messages
to be loaded into the receive registers. The masks can
be set to all zeros to provide a mode that accepts all
messages. The Loopback mode is activated by setting
the mode request bits in the CANCON register.
19.3.6 ERROR RECOGNITION MODE
The module can be set to ignore all errors and receive
any message. The Error Recognition mode is activated
by setting the RXM<1:0> bits in the RXBnCON regis-
ters to 11. In this mode, the data which is in the mes-
sage assembly buffer until the error time, is copied in
the receive buffer and can be read via the CPU inter-
face. In addition, the data which was on the internal
sampling of the CAN bus at the error time and the state
vector of the protocol state machine and the bit counter
CntCan, are stored in registers and can be read.
19.4 CAN Message Transmission
19.4.1 TRANSMIT BUFFERS
The PIC18FXX8 implements three Transmit Buffers
(Figure 19-2). Each of these buffers occupies 14 bytes
of SRAM and are mapped into the device memory
map.
For the MCU to have write access to the message
buffer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the TXBnSIDH, TXBnSIDL,
and TXBnDLC registers must be loaded. If data bytes
are present in the message, the TXBnDm registers
must also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the EXIDE bit set.
Prior to sending the message, the MCU must initialize
the TXInE bit to enable or disable the generation of an
interrupt when the message is sent. The MCU must
also initialize the TXP priority bits (see Section 19.4.2).
PIC18FXX8
19.4.2 TRANSMIT PRIORITY
Transmit priority is a prioritization within the PIC18FXX8
of the pending transmittable messages. This is indepen-
dent from, and not related to, any prioritization implicit in
the message arbitration scheme built into the CAN pro-
tocol. Prior to sending the SOF, the priority of all buffers
that are queued for transmission is compared. The trans-
mit buffer with the highest priority will be sent first. If two
buffers have the same priority setting, the buffer with the
highest buffer number will be sent first. There are four
levels of transmit priority. If TXP bits for a particular mes-
sage buffer are set to 11, that buffer has the highest pos-
sible priority. If TXP bits for a particular message buffer
are 00, that buffer has the lowest possible priority.
FIGURE 19-2:
TRANSMIT BUFFER
BLOCK DIAGRAM
Message
Request
Message
Queue
Control
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB0
MESSAGE
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB1
MESSAGE
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB2
MESSAGE
Transmit Byte Sequencer
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 223