PIC18F258 Datasheet, PDF (350/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
TABLE 27-18: I²C BUS DATA REQUIREMENTS (SLAVE MODE)
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock high time 100 kHz mode
4.0
— µs PIC18FXX8 must operate
at a minimum of 1.5 MHz
400 kHz mode
0.6
— µs PIC18FXX8 must operate
at a minimum of 10 MHz
101
TLOW
102 TR
Clock low time
SSP Module
100 kHz mode
1.5 TCY
—
4.7
—
400 kHz mode
1.3
—
SDA and SCL rise
time
SSP module
100 kHz mode
400 kHz mode
1.5 TCY
—
20 + 0.1 CB
—
1000
300
µs PIC18FXX8 must operate
at a minimum of 1.5 MHz
µs PIC18FXX8 must operate
at a minimum of 10 MHz
ns
ns
ns CB is specified to be from
10 to 400 pF
103 TF
SDA and SCL fall 100 kHz mode
—
300
time
400 kHz mode 20 + 0.1 CB 300
ns
ns CB is specified to be from
10 to 400 pF
90
TSU:STA START condition 100 kHz mode
4.7
— µs Only relevant for Repeated
setup time
400 kHz mode
0.6
—
µs ^{START condition}
91
THD:STA START condition 100 kHz mode
4.0
— µs After this period the first
hold time
400 kHz mode
0.6
—
µs ^{clock pulse is generated}
106
THD:DAT Data input hold
100 kHz mode
time
400 kHz mode
107 TSU:DAT Data input setup 100 kHz mode
time
400 kHz mode
92
TSU:STO STOP condition 100 kHz mode
setup time
400 kHz mode
109 TAA
Output valid from 100 kHz mode
clock
400 kHz mode
110
TBUF
Bus free time
100 kHz mode
400 kHz mode
0
—
ns
0
0.9 µs
250
—
ns (Note 2)
100
—
ns
4.7
— µs
0.6
— µs
—
3500 ns (Note 1)
—
—
ns
4.7
— µs Time the bus must be free
1.3
—
µs ^{before a new transmission}
can start
D102 CB
Bus capacitive loading
—
400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement
TSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line.
Before the SCL line is released, TR max. + TSU;DAT = 1000 + 250 = 1250 ns (according to the Standard
mode I²C bus specification).
DS41159B-page 348
Preliminary
 2002 Microchip Technology Inc.