PIC18F258 Datasheet, PDF (28/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
3.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected. To take advantage of the POR cir-
cuitry, connect the MCLR pin directly (or through a
resistor) to VDD. This eliminates external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified (refer to
parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met. Brown-out Reset may be used to meet
the voltage start-up condition.
3.2 MCLR
PIC18FXX8 devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both resets and current draws outside of
device specification during the RESET event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC18FXX8
R1
1 kΩ (or greater)
C1
0.1 µF
(not critical)
MCLR
3.3 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows VDD to rise to an
acceptable level. A configuration bit (PWRTEN in
CONFIG2L register) is provided to enable/disable the
PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.4 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This additional
delay ensures that the crystal oscillator or resonator
has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from SLEEP.
3.5 PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator
start-up time-out (OST).
3.6 Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set), the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation resets the
chip. A RESET may not occur if VDD falls below param-
eter D005 for less than parameter #35. The chip will
remain in Brown-out Reset until VDD rises above BVDD.
The Power-up Timer will then be invoked and will keep
the chip in RESET an additional time delay (parameter
#33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
DS41159B-page 26
Preliminary
 2002 Microchip Technology Inc.