PIC18F258 Datasheet, PDF (134/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
16.4 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP mod-
ule in PWM mode, as described in Section 15.4. The
differences in registers and ports are as described in
Section 16.2; in addition, the two Least Significant bits
of the 10-bit PWM duty cycle value are represented by
ECCP1CON<5:4>.
Note:
When setting up single output PWM opera-
tions, users are free to use either of the pro-
cesses described in Section 15.4.3 or
Section 16.5.8. The latter is more generic,
but will work for either single or multi-output
PWM.
16.5 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is an upwardly compatible version of
the standard CCP module and is modified to provide up
to four outputs, designated P1A through P1D. Users
are also able to select the polarity of the signal (either
active high or active low). The module’s Output mode
and polarity are configured by setting the
EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits
of the ECCP1CON register (ECCP1CON<7:6> and
ECCP1CON<3:0>, respectively).
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when the assigned timer resets), in
order to prevent glitches on any of the outputs. The
exception is the PWM delay register ECCP1DEL,
which is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets, instead of starting immediately. This means that
enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).
As before, the user must manually configure the appro-
priate TRISD bits for output.
16.5.1 PWM OUTPUT CONFIGURATIONS
The EPWM1M<1:0> bits in the ECCP1CON register
allow one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 15.4. The Half-Bridge and Full-
Bridge Output modes are covered in detail in the
sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
FIGURE 16-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Duty Cycle Registers
ECCPR1L
ECCP1CON<5:4>
EPWM1M1<1:0>
2
ECCP1M<3:0>
4
ECCP1/P1A
TRISD<4>
ECCPR1H (Slave)
Comparator
TMR2
(Note 1)
RQ
S
P1B
Output
Controller
P1C
TRISD<5>
TRISD<6>
Comparator
PR2
Clear Timer,
set ECCP1 pin and
latch D.C.
P1D
ECCP1DEL
TRISD<7>
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time-base.
DS41159B-page 132
Preliminary
 2002 Microchip Technology Inc.