PIC18F258 Datasheet, PDF (107/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

10.0 PARALLEL SLAVE PORT
Note: The Parallel Slave Port is only available on
PIC18F4X8 devices.
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port. PSP operation is con-
trolled by the 4 upper bits of the TRISE register
(Register 9-1). Setting control bit PSPMODE
(TRISE<4>) enables PSP operation. In Slave mode,
the port is asynchronously readable and writable by the
external world.
The PSP can directly interface to an 8-bit microproces-
sor data bus. The external microprocessor can read or
write the PORTD latch as an 8-bit latch. Setting the
control bit PSPMODE enables the PORTE I/O pins to
become control inputs for the microprocessor port.
When set, port pin RE0 is the RD input, RE1 is the WR
input, and RE2 is the CS (chip select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The timing for the control signals in write and read
modes is shown in Figure 10-2 and Figure 10-3,
respectively.
PIC18FXX8
FIGURE 10-1:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
Data Bus
One bit of PORTD
DQ
WR LATD
or
CK
WR PORTD
Data Latch
TTL
RDx pin
Q
D
RD PORTD
ENEN
RD LATD
Set Interrupt Flag
PSPIF (PIR1<7>)
PORTE pins
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pins have diode protection to VDD and VSS.
FIGURE 10-2:
PARALLEL SLAVE PORT WRITE WAVEFORMS
CS
WR
RD
PORTD
IBF
OBF
PSPIF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 105