PIC18F258 Datasheet, PDF (51/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
TABLE 4-2: REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR Page:
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
STKFUL STKUNF
—
Return Stack Pointer
00-0 0000
—
—
bit21⁽²⁾ Holding Register for PC<20:16>
---0 0000
Holding Register for PC<15:8>
0000 0000
PC Low Byte (PC<7:0>)
—
—
0000 0000
bit21⁽²⁾ Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) _{--00 0000}
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
Program Memory Table Latch
0000 0000
Product Register High Byte
xxxx xxxx
Product Register Low Byte
xxxx xxxx
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF 0000 000x
RBPU INTEDG0 INTEDG1
—
—
TMR0IP
—
RBIP 111- -1-1
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF INT1IF 11-1 0-00
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a
Uses contents of FSR0 to address data memory - value of FSR0 offset by W (not a physical register)
n/a
—
—
—
—
Indirect Data Memory Address Pointer 0 High ---- xxxx
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
Working Register
uuuu uuuu
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
n/a
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a
Uses contents of FSR1 to address data memory - value of FSR1 offset by W (not a physical register) -
n/a
—
—
—
—
Indirect Data Memory Address Pointer 1 High ---- xxxx
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
—
—
—
—
Bank Select Register
---- 0000
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
n/a
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a
Uses contents of FSR2 to address data memory - value of FSR2 offset by W (not a physical register) -
n/a
—
—
—
—
Indirect Data Memory Address Pointer 2 High ---- xxxx
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
—
—
—
N
OV
Z
DC
C
---x xxxx
Timer0 Register High Byte
0000 0000
Timer0 Register Low Byte
xxxx xxxx
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2 T0PS1 T0PS0 1111 1111
—
—
—
—
—
—
—
SCS ---- ---0
—
—
IRVST
LVDEN
LVDL3
LVDL2 LVDL1 LVDL0 --00 0101
—
—
—
—
—
—
—
SWDTEN ---- ---0
30, 38
30, 38
30, 38
30, 39
30, 40
30, 40
30, 40
30, 68
30, 68
30, 68
30, 68
30, 75
30, 75
30, 79
30, 80
30, 81
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
31, 55
31, 55
31, 54
31, 55
31, 55
31, 55
31, 55
31, 55
31, 55
31, 55
31, 57
31, 109
31, 109
31, 107
31, 20
31, 257
31, 268
RCON
IPEN
—
—
RI
TO
PD
POR
BOR 0--1 11qq 31, 58, 91
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.
2: Bit21 of the TBLPTRU allows access to the device configuration bits.
3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator
modes.
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 49