PIC18F258 Datasheet, PDF (340/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
TABLE 27-7: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
Param No. Symbol
Characteristic
7
TPLL PLL Start-up Time (Lock Time)
∆CLK CLKO Stability (Jitter) using PLL
Min
—
TBD
Max
2
TBD
Units
ms
%
Conditions
FIGURE 27-6:
OSC1
CLKO AND I/O TIMING
Q4
Q1
10
Q2
Q3
11
CLKO
13
14
I/O Pin
(Input)
17
I/O Pin
(Output)
Old Value
20, 21
Note: Refer to Figure 27-4 for load conditions.
19
18
15
12
16
New Value
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10
TosH2ckL OSC1↑ to CLKO↓
—
75
200
ns
(1)
11
TosH2ckH OSC1↑ to CLKO↑
—
75
200
ns
(1)
12
TckR
CLKO rise time
—
35
100
ns
(1)
13
TckF
CLKO fall time
—
35
100
ns
(1)
14
TckL2ioV CLKO ↓ to Port out valid
—
— 0.5 TCY + 20 ns
(1)
15
TioV2ckH Port in valid before CLKO↑
0.25 TCY + 25 —
—
ns
(1)
16
TckH2ioI Port in hold after CLKO↑
0
—
—
ns
(1)
17
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18
TosH2ioI OSC1↑ (Q2 cycle) to Port PIC18FXX8
100
—
—
ns
18A
input invalid (I/O in hold time) _PIC18LFXX8
200
—
—
ns
19
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20
TIOR
Port output rise time
PIC18FXX8
—
10
25
ns
20A
PIC18LFXX8
—
—
60
ns
21
TIOF
Port output fall time
PIC18FXX8
—
10
25
ns
21A
PIC18LFXX8
—
—
60
ns
22†† TINP
INT pin high or low time
TCY
—
—
ns
23†† TRBP
RB7:RB4 change INT high or low time
TCY
—
—
ns
24†† TRCP
RC7:RC4 change INT high or low time
20
—
—
ns
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC.
DS41159B-page 338
Preliminary
 2002 Microchip Technology Inc.