PIC18F258 Datasheet, PDF (240/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 20-2: ADCON1 REGISTER
R/W-0 R/W-0
U-0
ADFM ADCS2
—
bit 7
U-0
R/W-0 R/W-0 R/W-0 R/W-0
—
PCFG3 PCFG2 PCFG1 PCFG0
bit 0
bit 7 ADFM: A/D Result Format Select bit.
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
ADCON1
ADCON0
<ADCS2> <ADCS1:ADCS0>
Clock Conversion
0
00
FOSC/2
0
01
FOSC/8
0
10
FOSC/32
0
11
FRC (clock derived from the internal A/D RC oscillator)
1
00
FOSC/4
1
01
FOSC/16
1
10
FOSC/64
1
11
FRC (clock derived from the internal A/D RC oscillator)
bit 5-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF-
0000 A
A
A
A
A
A
A
A
VDD
VSS
0001 A
A
A
A
VREF+
A
A
A
AN3
VSS
0010 D
D
D
A
A
A
A
A
VDD
VSS
0011 D
D
D
A
VREF+
A
A
A
AN3
VSS
0100 D
D
D
D
A
D
A
A
VDD
VSS
0101 D
D
D
D
VREF+
D
A
A
AN3
VSS
011x D
D
D
D
D
D
D
D
—
—
1000 A
A
A
A VREF+ VREF- A
A
AN3 AN2
1001 D
D
A
A
A
A
A
A
VDD
VSS
1010 D
D
A
A
VREF+
A
A
A
AN3
VSS
1011 D
D
A
A VREF+ VREF- A
A
AN3 AN2
1100 D
D
D
A VREF+ VREF- A
A
AN3 AN2
1101 D
D
D
D VREF+ VREF- A
A
AN3 AN2
1110 D
D
D
D
D
D
D
A
VDD
VSS
1111 D
D
D
D VREF+ VREF- D
A
AN3 AN2
A = Analog input D = Digital I/O
C / R = # of analog input channels / # of A/D voltage references
Note: Shaded cells indicate channels available only on PIC18F4X8 devices.
C/R
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx)
are forced to be analog inputs.
DS41159B-page 238
Preliminary
 2002 Microchip Technology Inc.