PIC18F258 Datasheet, PDF (222/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 19-35: IPR3 – PERIPHERAL INTERRUPT PRIORITY REGISTER
R/W-1
IRXIP
bit 7
R/W-1
WAKIP
R/W-1
ERRIP
R/W-1
TXB2IP
R/W-1
TXB1IP
R/W-1
TXB0IP
R/W-1
RXB1IP
R/W-1
RXB0IP
bit 0
bit 7
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
ERRIP: CAN bus Error Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS41159B-page 220
Preliminary
 2002 Microchip Technology Inc.