PIC18F258 Datasheet, PDF (115/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
12.2 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON register). The
oscillator is a low power oscillator rated up to 200 kHz.
It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
TABLE 12-1: CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
Osc Type
Freq
C1
LP
32 kHz
TBD⁽¹⁾
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
C2
TBD⁽¹⁾
± 20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
4: Capacitor values are for design guidance
only.
12.3 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The TMR1
Interrupt, if enabled, is generated on overflow, which is
latched in interrupt flag bit TMR1IF (PIR registers). This
interrupt can be enabled/disabled by setting/clearing
TMR1 interrupt enable bit TMR1IE (PIE registers).
12.4 Resetting Timer1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0 =
‘1011’), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR registers).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a special
event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers
pair, effectively becomes the period register for Timer1.
12.5 Timer1 16-bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit (T1CON
register) is set, the address for TMR1H is mapped to a
buffer register for the high byte of Timer1. A read from
TMR1L will load the contents of the high byte of Timer1
into the Timer1 high byte buffer. This provides the user
with the ability to accurately read all 16 bits of Timer1,
without having to determine whether a read of the high
byte, followed by a read of the low byte is valid, due to
a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 113