PIC18F258 Datasheet, PDF (25/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
2.7 Effects of SLEEP Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.8 Power-up Delays
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see Section 3.0.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of TPWRT (parameter
#D033) on power-up only (POR and BOR). The second
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in RESET until the crystal oscillator is
stable.
With the PLL enabled (HS4 Oscillator mode), the time-
out sequence following a Power-on Reset is different
from other Oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a suf-
ficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional time-out. This time is called TPLL (parameter
#7) to allow the PLL ample time to lock to the incoming
clock frequency.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC
RCIO
ECIO
EC
LP, XT, and HS
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating
Floating
Feedback inverter disabled, at quiescent
voltage level
At logic low
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low
Feedback inverter disabled, at quiescent
voltage level
Note: See Table 3-1 in Section 3.0, for time-outs due to SLEEP and MCLR Reset.
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 23