PIC18F258 Datasheet, PDF (140/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
16.5.4 PROGRAMMABLE DEADBAND
DELAY
In half-bridge or full-bridge applications, where all
power switches are modulated at the PWM frequency
at all times, the power switches normally require longer
time to turn off than to turn on. If both the upper and
lower power switches are switched at the same time
(one turned on, and the other turned off), both switches
will be on for a short period of time until one switch
completely turns off. During this time, a very high cur-
rent (shoot-through current) flows through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on the power switch is nor-
mally delayed to allow the other switch to completely
turn off.
In the Half-Bridge Output mode, a digitally program-
mable deadband delay is available to avoid shoot-
through current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 16-3
for illustration. The ECCP1DEL register (Register 16-2)
sets the amount of delay.
16.5.5 SYSTEM IMPLEMENTATION
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller powers up, all of the I/O pins
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
devices in the off state, until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
16.5.6 START-UP CONSIDERATIONS
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISD bits for output at the same time
with the ECCP1 module may cause damage to the
power switch devices. The ECCP1 module must be
enabled in the proper Output mode with the TRISD bits
enabled as inputs. Once the ECCP1 completes a full
PWM cycle, the P1A, P1B, P1C and 1PD output
latches are properly initialized. At this time, the TRISD
bits can be enabled for outputs to start driving the
power switch devices. The completion of a full PWM
cycle is indicated by the TMR2IF bit going from a ’0’ to
a ’1’.
16.5.7 OUTPUT POLARITY
CONFIGURATION
The ECCP1M<1:0> bits in the ECCP1CON register
allow user to choose the logic conventions (asserted
high/low) for each of the outputs.
The PWM output polarities must be selected before the
PWM outputs are enabled. Charging the polarity con-
figuration while the PWM outputs are active is not rec-
ommended, since it may result in unpredictable
operation.
REGISTER 16-2: ECCP1DEL REGISTER
R/W-0
EPDC7
bit 7
R/W-0
EPDC6
R/W-0
EPDC5
R/W-0
EPDC4
R/W-0
EPDC3
R/W-0
EPDC2
R/W-0
EPDC1
R/W-0
EPDC0
bit 0
bit 7-0
EPDC<7:0>: PWM Delay Count for Half-Bridge Output Mode bits
Number of FOSC/4 (TOSC*4) cycles between the P1A transition and the P1B transition
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS41159B-page 138
Preliminary
 2002 Microchip Technology Inc.