PIC18F258 Datasheet, PDF (371/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

INDEX
A
A/D ................................................................................... 237
A/D Converter Flag (ADIF bit) .................................. 239
A/D Converter Interrupt, Configuring ....................... 240
Acquisition Requirements ........................................ 240
Acquisition Time ....................................................... 241
ADCON0 Register .................................................... 237
ADCON1 Register .................................................... 237
ADRESH Register .................................................... 237
ADRESH/ADRESL Registers .................................. 239
ADRESL Register .................................................... 237
Analog Port Pins, Configuring .................................. 242
Associated Registers Summary ............................... 243
Calculating the Minimum Required
Acquisition Time ............................................... 241
Configuring the Module ............................................ 240
Conversion Clock (TAD) ........................................... 242
Conversion Status (GO/DONE bit) .......................... 239
Conversion TAD Cycles ............................................ 243
Conversions ............................................................. 243
Converter Characteristics ........................................ 352
Minimum Charging Time .......................................... 241
Selecting the Conversion Clock ............................... 242
Special Event Trigger (CCP) .................................... 124
Special Event Trigger (ECCP) ......................... 131, 243
TAD vs. Device Operating Frequencies
(For Extended, LC Devices) (table) ................. 242
TAD vs. Device Operating Frequencies (table) ........ 242
Use of the ECCP Trigger ......................................... 243
Absolute Maximum Ratings ............................................. 325
AC (Timing) Characteristics ............................................. 335
Parameter Symbology ............................................. 335
Access Bank ...................................................................... 54
ACKSTAT ......................................................................... 171
ADCON0 Register ............................................................ 237
GO/DONE bit ........................................................... 239
ADCON1 Register ............................................................ 237
ADDLW ............................................................................ 283
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART
ADDWF ............................................................................ 283
ADDWFC ......................................................................... 284
ADRESH Register ............................................................ 237
ADRESH/ADRESL Registers ........................................... 239
ADRESL Register ............................................................ 237
Analog-to-Digital Converter. See A/D
ANDLW ............................................................................ 284
ANDWF ............................................................................ 285
Assembler
MPASM Assembler .................................................. 319
Associated Registers ............................................... 190, 195
B
Bank Select Register (BSR) ............................................... 54
Baud Rate Generator ....................................................... 167
BC .................................................................................... 285
BCF .................................................................................. 286
BF ..................................................................................... 171
Bit Timing Configuration Registers
BRGCON1 ............................................................... 232
BRGCON2 ............................................................... 232
BRGCON3 ............................................................... 232
PIC18FXX8
Block Diagrams
A/D ........................................................................... 239
Analog Input Model ...........................................240, 249
Baud Rate Generator .............................................. 167
CAN Buffers and Protocol Engine ........................... 198
Capture Mode (CCP Module) .................................. 123
Comparator I/O Operating Modes ........................... 246
Comparator Output .................................................. 248
Compare (CCP Module) Mode Operation ............... 124
Enhanced PWM ....................................................... 132
Interrupt Logic ............................................................ 78
Low Voltage Detect ................................................. 256
Low Voltage Detect with External Input ................... 256
MSSP (I²C Master Mode) ........................................ 165
MSSP (I²C Mode) .................................................... 150
MSSP (SPI Mode) ................................................... 141
On-Chip Reset Circuit ................................................ 25
PIC18F248/258 Architecture ....................................... 8
PIC18F448/458 Architecture ....................................... 9
PLL ............................................................................ 19
PORTC (Peripheral Output Override) ........................ 98
PORTD and PORTE (Parallel Slave Port) ............... 105
PORTD in I/O Port Mode ......................................... 100
PORTE .................................................................... 102
PWM (CCP Module) ................................................ 126
RA3:RA0 and RA5 Port Pins ..................................... 93
RA4/T0CKI Pin .......................................................... 93
RA6/OSC2/CLKO Pin ................................................ 94
RB1:RB0 Port Pins .................................................... 95
RB2:CANTX Port Pins ............................................... 96
RB3:CANRX Port Pins ............................................... 96
RB7:RB4 Port Pins .................................................... 95
Reads from FLASH Program Memory ....................... 69
Receive Buffer ......................................................... 226
Table Read Operation ............................................... 65
Table Write Operation ................................................ 66
Table Writes to FLASH Program Memory ................. 71
Timer0 Module
16-bit Mode ...................................................... 108
8-bit Mode ........................................................ 108
Timer1 Module ......................................................... 112
Timer1 Module (16-bit Read/Write Mode) ............... 112
Timer2 ..................................................................... 116
Timer3 ..................................................................... 118
Timer3 (16-bit Read/Write Mode) ............................ 118
Transmit Buffer ........................................................ 223
USART Receive ....................................................... 189
USART Transmit ...................................................... 187
Voltage Reference ................................................... 252
Watchdog Timer ...................................................... 269
BN .................................................................................... 286
BNC ................................................................................. 287
BNN ................................................................................. 287
BNOV ............................................................................... 288
BNZ .................................................................................. 288
BOR. See Brown-out Reset
BOV ................................................................................. 291
BRA ................................................................................. 289
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 369