PIC18F258 Datasheet, PDF (96/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
FIGURE 9-3:
RA6/OSC2/CLKOUT PIN BLOCK DIAGRAM
(FOSC = 101, 111)
CLKO (FOSC/4)
1
Data Latch
Data Bus
D
Q
0
From OSC1
Oscillator
Circuit
VDD
WR PORTA
CK Q
P
TRIS Latch
D
Q
N
WR TRISA
CK Q
(FOSC = 100,
101, 110, 111)
VSS
RD TRISA
RD PORTA
(FOSC = 110, 100)
DQata LatcDh
EN
Note 1: CLKO is 1/4 of FOSC.
2: I/O pin has diode protection to VDD and VSS.
Schmitt
Trigger
Input Buffer
RA6/OSC2/
CLKO pin⁽²⁾
TABLE 9-1: PORTA FUNCTIONS
Name
Bit# Buffer
Function
RA0/AN0/CVREF
bit0
TTL Input/output, analog input, or analog comparator voltage reference
output.
RA1/AN1
bit1 TTL Input/output or analog input.
RA2/AN2/VREF-
bit2
TTL Input/output, analog input or VREF-.
RA3/AN3/VREF+
bit3
TTL Input/output, analog input or VREF+.
RA4/T0CKI
bit4 ST/OD Input/output, external clock input for Timer0, output is open drain type.
RA5/SS/AN4/LVDIN
bit5 TTL Input/output, slave select input for synchronous serial port, analog input,
or low voltage detect input.
RA6/OSC2/CLKO
bit6
TTL Input/output or oscillator clock output.
Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain
TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
PORTA
— RA6 RA5 RA4 RA3
RA2
RA1
RA0 -00x 0000 -uuu uuuu
LATA
— Latch A Data Output Register
-xxx xxxx -uuu uuuu
TRISA
— PORTA Data Direction Register
-111 1111 -111 1111
ADCON1 ADFM ADCS2 —
— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 uu-- uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS41159B-page 94
Preliminary
 2002 Microchip Technology Inc.