PIC18F258 Datasheet, PDF (345/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
FIGURE 27-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
78
79
SDO
80
MSb
79
78
Bit6 - - - - - -1
LSb
SDI
MSb In
74
73
Note: Refer to Figure 27-4 for load conditions.
75, 76
Bit6 - - - -1
LSb In
TABLE 27-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A TB2B
Last clock edge of Byte1 to the 1st clock edge of 1.5 TCY + 40 —
Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time PIC18FXX8
—
25
PIC18LFXX8
—
45
76
TdoF
SDO data output fall time
—
25
78
TscR
SCK output rise time
(Master mode)
PIC18FXX8
PIC18LFXX8
—
25
—
45
79
TscF
SCK output fall time (Master mode)
—
25
80
TscH2doV, SDO data output valid after PIC18FXX8
TscL2doV SCK edge
PIC18LFXX8
—
50
—
100
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #’s 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 343