PIC18F258 Datasheet, PDF (233/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

19.8 Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Sync
Seg). The circuit will then adjust the values of phase
segment 1 and phase segment 2, as necessary. There
are two mechanisms used for synchronization.
19.8.1 HARD SYNCHRONIZATION
Hard synchronization is only done when there is a
recessive to dominant edge during a BUS IDLE condi-
tion, indicating the start of a message. After hard syn-
chronization, the bit time counters are restarted with
Sync Seg. Hard synchronization forces the edge which
has occurred to lie within the synchronization segment
of the restarted bit time. Due to the rules of synchroni-
zation, if a hard synchronization occurs, there will not
be a resynchronization within that bit time.
19.8.2 RESYNCHRONIZATION
As a result of resynchronization, phase segment 1 may
be lengthened, or phase segment 2 may be shortened.
The amount of lengthening or shortening of the phase
buffer segments has an upper bound given by the Syn-
chronization Jump Width (SJW). The value of the SJW
will be added to phase segment 1 (see Figure 19-8), or
subtracted from phase segment 2 (see Figure 19-9).
The SJW is programmable between 1 TQ and 4 TQ.
Clocking information will only be derived from reces-
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
PIC18FXX8
The phase error of an edge is given by the position of
the edge relative to Sync Seg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
• e = 0 if the edge lies within SYNCESEG.
• e > 0 if the edge lies before the SAMPLE POINT.
• e < 0 if the edge lies after the SAMPLE POINT of
the previous bit
If the magnitude of the phase error is less than, or equal
to, the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width, and if the phase error is
positive, then phase segment 1 is lengthened by an
amount equal to the synchronization jump width.
If the magnitude of the phase error is larger than the
resynchronization jump width, and if the phase error is
negative, then phase segment 2 is shortened by an
amount equal to the synchronization jump width.
19.8.3 SYNCHRONIZATION RULES
• Only one synchronization within one bit time is
allowed.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges fulfilling
rules 1 and 2, will be used for resynchronization,
with the exception that a node transmitting a dom-
inant bit will not perform a resynchronization as a
result of a recessive to dominant edge with a
positive phase error.
FIGURE 19-8:
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Input
Signal
Bit
Time
Sync
Segments
TQ
Prop
Segment
Phase
Segment 1
≤ SJW
Nominal Bit Length
Sample Point
Actual Bit Length
Phase
Segment 2
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 231