PIC18F258 Datasheet, PDF(245/384 Page) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

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PIC18F258 Datasheet, PDF (245/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

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PIC18FXX8

20.4 A/D Conversions

Figure 20-3 shows the operation of the A/D converter

after the GO bit has been set. Clearing the GO/DONE

bit during a conversion will abort the current conver-

sion. The A/D result register pair will NOT be updated

with the partially completed A/D conversion sample.

That is, the ADRESH:ADRESL registers will continue

to contain the value of the last completed conversion

(or the last value written to the ADRESH:ADRESL reg-

isters). After the A/D conversion is aborted, a 2 TAD wait

is required before the next acquisition is started. After

this 2 TAD wait, acquisition on the selected channel is

automatically started.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

20.5 Use of the ECCP Trigger

An A/D conversion can be started by the âspecial event

triggerâ of the ECCP module. This requires that the

ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro-

grammed as 1011 and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion and

the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location). The

appropriate analog input channel must be selected and

the minimum acquisition done before the âspecial event

triggerâ sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

âspecial event triggerâ will be ignored by the A/D module,

but will still reset the Timer1 (or Timer3) counter.

FIGURE 20-3:

A/D CONVERSION TAD CYCLES

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0

Conversion Starts

Holding capacitor is disconnected from analog input

(typically 100 ns)

Set GO bit

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

TABLE 20-3: SUMMARY OF A/D REGISTERS

Name Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

GIE/GIEH

PSPIF(1)

PSPIE(1)

PSPIP(1)

â

â

â

PEIE/GIEL

ADIF

ADIE

ADIP

CMIF(1)

CMIE(1)

CMIP(1)

TMR0IE

RCIF

RCIE

RCIP

â

â

â

ADRESH A/D Result Register

ADRESL A/D Result Register

INT0IE

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

RBIE

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

LVDIF

LVDIE

LVDIP

INT0IF

RBIF 0000 000x 0000 000u

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP

TMR3IF

TMR3IE

TMR3IP

TMR1IP 0000 0000

ECCP1IF(1) -0-0 0000

ECCP1IE(1) -0-0 0000

ECCP1IP(1) -0-0 0000

0000 0000

-0-0 0000

-0-0 0000

-0-0 0000

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE â

ADON 0000 00-0 0000 00-0

ADCON1 ADFM ADCS2

â

â

PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000

PORTA

â

RA6

RA5

RA4

RA3

RA2

RA1

RA0 -00x 0000 -00u 0000

TRISA

â PORTA Data Direction Register

-111 1111 -111 1111

PORTE

â

â

â

â

â

RE2

RE1

RE0 ---- -000 ---- -000

LATE

â

â

â

â

â

LATE2 LATE1

LATE0 ---- -xxx ---- -uuu

TRISE

IBF

OBF

IBOV PSPMODE â TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented, read as â0â. Shaded cells are not used for A/D conversion.

Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.

ï£© 2002 Microchip Technology Inc.

Preliminary

DS41159B-page 243

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