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PIC18F258 Datasheet, PDF (294/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN | |||
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PIC18FXX8
BZ
Branch if Zero
Syntax:
Operands:
Operation:
Status Affected:
[ label ] BZ n
-128 ⤠n ⤠127
if Zero bit is â1â
(PC) + 2 + 2n â PC
None
Encoding:
Description:
1110 0000 nnnn nnnn
If the Zero bit is â1â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Decode
Read literal
ânâ
No
operation
No
operation
If No Jump:
Q1
Q2
Decode
Read literal
ânâ
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Zero
=
PC
=
If Zero
=
PC
=
BZ Jump
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
CALL
Subroutine Call
Syntax:
[ label ] CALL k [,s]
Operands:
0 ⤠k ⤠1048575
s â [0,1]
Operation:
(PC) + 4 â TOS,
k â PC<20:1>,
if s = 1
(W) â WS,
(STATUS) â STATUSS,
(BSR) â BSRS
Status Affected: None
Encoding:
1st word (k<7:0>) 1110
2nd word(k<19:8>) 1111
110s k7kkk
k19kkk kkkk
kkkk0
kkkk8
Description:
Subroutine call of entire 2 Mbyte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If âsâ = 1, the W,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then, the 20-bit
value âkâ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
Read literal
âkâ<7:0>,
No
operation
No
operation
Q3
Push PC to
stack
No
operation
Q4
Read literal
âkâ<19:8>,
Write to PC
No
operation
Example:
HERE
CALL THERE,FAST
Before Instruction
PC
= address (HERE)
After Instruction
PC
=
TOS =
WS
=
BSRS =
STATUSS=
address (THERE)
address (HERE + 4)
W
BSR
STATUS
DS41159B-page 292
 2002 Microchip Technology Inc.
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