PIC18F258 Datasheet, PDF (219/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 19-31: BRGCON3 – BAUD RATE CONTROL REGISTER 3
U-0 R/W-0 U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
— WAKFIL —
—
— SEG2PH2⁽¹⁾ SEG2PH1⁽¹⁾ SEG2PH0⁽¹⁾
bit 7
bit 0
bit 7
bit 6
bit 5-3
bit 2-0
Unimplemented: Read as ’0’
WAKFIL: Selects CAN bus Line Filter for Wake-up bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
Unimplemented: Read as ’0’
SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits⁽¹⁾
111 = Phase Segment 2 Time = 8 x TQ
110 = Phase Segment 2 Time = 7 x TQ
101 = Phase Segment 2 Time = 6 x TQ
100 = Phase Segment 2 Time = 5 x TQ
011 = Phase Segment 2 Time = 4 x TQ
010 = Phase Segment 2 Time = 3 x TQ
001 = Phase Segment 2 Time = 2 x TQ
000 = Phase Segment 2 Time = 1 x TQ
Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is clear.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
19.2.5 CAN MODULE I/O CONTROL
REGISTER
This register controls the operation of the CAN module’s
I/O pins in relation to the rest of the microcontroller.
REGISTER 19-32: CIOCON – CAN I/O CONTROL REGISTER
U-0
U-0
R/W-0 R/W-0
U-0
U-0
U-0
U-0
—
—
ENDRHI CANCAP
—
—
—
—
bit 7
bit 0
bit 7-6
bit 5
bit 4
bit 3-0
Unimplemented: Read as ‘0’
ENDRHI: Enable Drive High bit
1 = CANTX pin will drive VDD when recessive
0 = CANTX pin will tri-state when recessive
CANCAP: CAN Message Receive Capture Enable bit
1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1
0 = Disable CAN capture, RC2/CCP1 input to CCP1 module
Unimplemented: Read as ’0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 217