PIC18F258 Datasheet, PDF (151/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
17.3.8 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to
transmit/receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.
17.3.9 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
1
0
0
1
1
1
0
There is also a SMP bit, which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF
PSPIF
ADIF
RCIF TXIF SSPIF CCP1IF
PSPIE
ADIE
RCIE TXIE SSPIE CCP1IE
PSPIP
ADIP
RCIP TXIP SSPIP CCP1IP
PORTC Data Direction Register
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3 SSPM2
INT0IF
TMR2IF
TMR2IE
TMR2IP
TRISF1
SSPM1
RBIF
TMR1IF
TMR1IE
TMR1IP
TRISF0
SSPM0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0111 1111 0111 1111
1111 1111 1111 1111
1111 1111 uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the MSSP in SPI mode.
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 149