PIC18F258 Datasheet, PDF (347/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
FIGURE 27-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
83
78
79
79
78
Bit6 - - - - - -1
LSb
75, 76
SDI
MSb In
Bit6 - - - -1
74
73
Note: Refer to Figure 27-4 for load conditions.
77
LSb In
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
71 TscH
SCK input high time (Slave mode) Continuous
1.25 TCY + 30 —
71A
Single Byte
40
—
72 TscL
SCK input low time (Slave mode) Continuous
1.25 TCY + 30 —
72A
Single Byte
40
—
73 TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
73A TB2B
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 —
74 TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75 TdoR
SDO data output rise time
PIC18FXX8
—
25
PIC18LFXX8
45
76 TdoF
SDO data output fall time
—
25
77 TssH2doZ SS↑ to SDO output hi-impedance
10
50
78 TscR
SCK output rise time (Master mode) PIC18FXX8
—
25
PIC18LFXX8
45
79 TscF
SCK output fall time (Master mode)
—
25
80 TscH2doV, SDO data output valid after SCK PIC18FXX8
TscL2doV edge
PIC18LFXX8
—
50
100
83 TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #’s 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 345