PIC18F258 Datasheet, PDF (52/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR Page:
TMR1H
TMR1L
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx 31, 113
xxxx xxxx 31, 113
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 31, 111
TMR2
Timer2 Register
0000 0000 31, 116
PR2
Timer2 Period Register
1111 1111 31, 116
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 31, 115
SSPBUF
SSPADD
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C Slave mode. SSP Baud Rate Reload Register in I²C Master mode.
xxxx xxxx 31, 144
0000 0000 31, 150
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 31, 142, 151
SSPCON1
WCOL
SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 31, 143, 152
SSPCON2
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 31, 153
ADRESH
A/D Result Register High Byte
xxxx xxxx 32, 239
ADRESL
A/D Result Register Low Byte
xxxx xxxx 32, 239
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0 GO/DONE —
ADON 0000 00-0 32, 237
ADCON1
ADFM
ADCS2
—
—
PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 32, 238
CCPR1H
Capture/Compare/PWM Register1 High Byte
xxxx xxxx 32, 122
CCPR1L
Capture/Compare/PWM Register1 Low Byte
xxxx xxxx 32, 122
CCP1CON
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 32, 121
ECCPR1H⁽¹⁾ Enhanced Capture/Compare/PWM Register1 High Byte
xxxx xxxx 32, 131
ECCPR1L⁽¹⁾ Enhanced Capture/Compare/PWM Register1 Low Byte
xxxx xxxx 32, 131
ECCP1CON⁽¹⁾ EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 32, 129
ECCP1DEL⁽¹⁾ EPDC7
EPDC6
EPDC5
EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 0000 0000 32, 138
ECCPAS⁽¹⁾ ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 32, 140
CVRCON⁽¹⁾
CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000 32, 251
CMCON⁽¹⁾
C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0000 32, 245
TMR3H
Timer3 Register High Byte
xxxx xxxx 32, 119
TMR3L
Timer3 Register Low Byte
xxxx xxxx 32, 119
T3CON
RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 32, 117
SPBRG
USART1 Baud Rate Generator
0000 0000 32, 183
RCREG
USART1 Receive Register
0000 0000 32, 189
TXREG
USART1 Transmit Register
0000 0000 32, 187
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 32, 181
RCSTA
SPEN
RX9
SREN
CREN
ADDEN FERR
OERR
RX9D 0000 000X 32, 182
EEADR
EEPROM Address Register
xxxx xxxx 32, 59
EEDATA
EEPROM Data Register
xxxx xxxx 32, 59
EECON2
EEPROM Control Register2 (not a physical register)
xxxx xxxx 32, 59
EECON1
EEPGD
CFGS
—
FREE
WRERR WREN
WR
RD xx-0 x000 32, 60, 67
IPR3
IRXIP
WAKIP
ERRIP
TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 32, 90
PIR3
IRXIF
WAKIF
ERRIF
TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 32, 84
PIE3
IPR2
PIR2
PIE2
IRXIE
—
—
—
WAKIE
CMIP
CMIF
CMIE
ERRIE
—
—
—
TXB2IE
EEIP
EEIF
EEIE
TXB1IE
BCLIP
BCLIF
BCLIE
TXB0IE
LVDIP
LVDIF
LVDIE
RXB1IE
TMR3IP
TMR3IF
TMR3IE
RXB0IE 0000 0000
ECCP1IP⁽¹⁾ -1-1 1111
ECCP1IF⁽¹⁾ -0-0 0000
ECCP1IE⁽¹⁾ -0-0 0000
32, 87
33, 89
33, 83
33, 86
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ’0’s.
2: Bit21 of the TBLPTRU allows access to the device configuration bits.
3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator
modes.
DS41159B-page 50
Preliminary
 2002 Microchip Technology Inc.