PIC18F258 Datasheet, PDF (209/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 19-10: TXBnDLC – TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS
U-0
R/W-x
U-0
—
TXRTR
—
bit 7
U-0
R/W-x R/W-x R/W-x
—
DLC3
DLC2
DLC1
R/W-x
DLC0
bit 0
bit 7
bit 6
bit 5-4
bit 3-0
Unimplemented: Read as ’0’
TXRTR: Transmission Frame Remote Transmission Request bit
1 = Transmitted message will have TXRTR bit set
0 = Transmitted message will have TXRTR bit cleared
Unimplemented: Read as ’0’
DLC3:DLC0: Data Length Code bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Data Length = 8 bytes
0111 = Data Length = 7 bytes
0110 = Data Length = 6 bytes
0101 = Data Length = 5 bytes
0100 = Data Length = 4 bytes
0011 = Data Length = 3 bytes
0010 = Data Length = 2 bytes
0001 = Data Length = 1 bytes
0000 = Data Length = 0 bytes
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
REGISTER 19-11: TXERRCNT – TRANSMIT ERROR COUNT REGISTER
R-0
TEC7
bit 7
R-0
TEC6
R-0
TEC5
R-0
TEC4
R-0
TEC3
R-0
TEC2
R-0
TEC1
R-0
TEC0
bit 0
bit 7-0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the
error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11
consecutive recessive bits, the counter value is cleared.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 207