PIC18F258 Datasheet, PDF (163/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
17.4.4.5 Clock Synchronization and
the CKP bit
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
assert the SCL line until an external I²C master device
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set, and all other devices
on the I²C bus have de-asserted SCL. This ensures
that a write to the CKP bit will not violate the minimum
high time requirement for SCL (see Figure 17-12).
FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
CKP
WR
SSPCON
DX
Master device
asserts clock
Master device
de-asserts clock
DX-1
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 161