PIC18F258 Datasheet, PDF (379/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

Bus Collision During a Repeated
START Condition (Case 1) .............................. 179
Bus Collision During a Repeated
START Condition (Case2) ............................... 179
Bus Collision During a STOP
Condition (Case 1) ........................................... 180
Bus Collision During a STOP
Condition (Case 2) ........................................... 180
Bus Collision During START
Condition (SCL = 0) ......................................... 178
Bus Collision During START
Condition (SDA Only) ....................................... 177
Bus Collision for Transmit and
Acknowledge .................................................... 176
Capture/Compare/PWM
(CCP1 and ECCP1) ......................................... 341
CLKO and I/O .......................................................... 338
Clock Synchronization ............................................. 161
External Clock .......................................................... 337
First START bit Timing ............................................. 169
I²C Bus Data ............................................................ 347
I²C Bus START/STOP bits ...................................... 347
I²C Master Mode (Reception, 7-bit Address) ........... 173
I²C Master Mode (Transmission, 7 or
10-bit Address) ................................................. 172
I²C Slave Mode (Transmission,
10-bit Address) ................................................. 159
I²C Slave Mode (Transmission,
7-bit Address) ................................................... 157
I²C Slave Mode SEN = 1 (Reception,
10-bit Address) ................................................. 163
I²C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................. 158
I²C Slave Mode with SEN = 0 (Reception,
7-bit Address) ................................................... 156
I²C Slave Mode with SEN = 1 (Reception,
7-bit Address) ................................................... 162
Low Voltage Detect .................................................. 258
Master SSP I²C Bus Data ........................................ 349
Master SSP I²C Bus START/STOP bits .................. 349
Parallel Slave Port (PIC18F248
and PIC18F458) ............................................... 342
Parallel Slave Port Read Waveforms ....................... 106
Parallel Slave Port Write Waveforms ....................... 105
Repeat START Condition ........................................ 170
RESET, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST), Power-up Timer
(PWRT) ............................................................ 339
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 164
Slave Synchronization ............................................. 147
Slow Rise Time (MCLR Tied to VDD
Via RC Network) ................................................ 29
SPI Master Mode (CKE = 0) .................................... 343
SPI Master Mode (CKE = 1) .................................... 344
SPI Mode (Master Mode) ......................................... 146
SPI Mode (Slave Mode with CKE = 0) ..................... 148
SPI Mode (Slave Mode with CKE = 1) ..................... 148
SPI Slave Mode (CKE = 0) ...................................... 345
SPI Slave Mode (CKE = 1) ...................................... 346
STOP Condition Receive or Transmit Mode ............ 175
Time-out Sequence on POR w/ PLL Enabled
(MCLR Tied to VDD Via RC Network) ................ 29
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 1 ....................... 28
PIC18FXX8
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 2 ...................... 28
Time-out Sequence on Power-up
(MCLR Tied to VDD Via RC Network) ................ 28
Timer0 and Timer1 External Clock .......................... 340
Transition Between Timer1 and OSC1
(HS with PLL) .................................................... 22
Transition Between Timer1 and OSC1
(HS, XT, LP) ...................................................... 21
Transition Between Timer1 and OSC1
(RC, EC) ............................................................ 22
Transition from OSC1 to Timer1 Oscillator ................ 21
USART Asynchronous Reception ............................ 190
USART Asynchronous Transmission ...................... 188
USART Asynchronous Transmission
(Back to Back) ................................................. 188
USART Synchronous Receive (Master/Slave) ........ 351
USART Synchronous Reception
(Master Mode, SREN) ..................................... 193
USART Synchronous Transmission ........................ 192
USART Synchronous Transmission
(Master/Slave) ................................................. 351
USART Synchronous Transmission
(Through TXEN) .............................................. 192
Wake-up from SLEEP via Interrupt .......................... 271
Timing Diagrams and Specifications ............................... 337
A/D Conversion Requirements ................................ 353
Capture/Compare/PWM Requirements
(CCP1 and ECCP1) ......................................... 341
CLKO and I/O Timing Requirements ....................... 338
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 343
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 344
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 345
Example SPI Slave Mode Requirements (CKE = 1) 346
External Clock Timing Requirements ...................... 337
I²C Bus Data Requirements (Slave Mode) .............. 348
I²C Bus START/STOP bits Requirements
(Slave Mode) ................................................... 347
Master SSP I²C Bus Data Requirements ................ 350
Master SSP I²C Bus START/STOP bits
Requirements .................................................. 349
Parallel Slave Port Requirements
(PIC18F248 and PIC18F458) .......................... 342
PLL Clock ................................................................ 338
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer, Brown-out Reset
and Low Voltage Detect Requirements ........... 339
Timer0 and Timer1 External
Clock Requirements ........................................ 340
USART Synchronous Transmission
Requirements .................................................. 351
TSTFSZ ........................................................................... 317
TXSTA Register
BRGH bit ................................................................. 183
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 377