PIC18F258 Datasheet, PDF (104/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
9.5 PORTE, TRISE and LATE
Registers
Note: This port is only available on the
PIC18F448 and PIC18F458.
PORTE is a 3-bit wide, bi-directional port. PORTE has
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT), which are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
Read-modify-write operations on the LATE register,
reads and writes the latched output value for PORTE.
The corresponding Data Direction register for the port
is TRISE. Setting a TRISE bit (= ‘1’) will make the cor-
responding PORTE pin an input (i.e., put the corre-
sponding output driver in a High-Impedance mode).
Clearing a TRISE bit (= ‘0’) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
The TRISE register also controls the operation of the
Parallel Slave Port, through the control bits in the upper
half of the register. These are shown in Register 9-1.
When the Parallel Slave Port is active, the PORTE pins
function as its control inputs. For additional details,
refer to Section 10.0.
PORTE pins are also multiplexed with inputs for the
A/D converter and outputs for the analog comparators.
When selected as an analog input, these pins will read
as '0's. Direction bits TRISE<2:0> control the direction
of the RE pins, even when they are being used as ana-
log inputs. The user must make sure to keep the pins
configured as inputs when using them as analog
inputs.
EXAMPLE 9-5:
CLRF PORTE
CLRF LATE
MOVLW 03h
MOVWF TRISE
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE2 as an output
; (RE4=0 - PSPMODE Off)
FIGURE 9-10:
PORTE BLOCK DIAGRAM
Peripheral Out Select
Peripheral Data Out
RD LATE
Data Bus
WR LATE
or
WR PORTE
WR TRISE
DQ
CK Q
Data Latch
DQ
CK Q
TRIS Latch
0
1
TRIS
Override
VDD
P
N
VSS
RD TRISE
Peripheral Enable
RD PORTE
Peripheral Data In
Schmitt
Trigger
Q
D
EN
Note 1: I/O pins have diode protection to VDD and VSS.
I/O pin⁽¹⁾
TRIS OVERRIDE
Pin Override Peripheral
RE0 Yes
RE1 Yes
RE2 Yes
PSP
PSP
PSP
DS41159B-page 102
Preliminary
 2002 Microchip Technology Inc.