PIC18F258 Datasheet, PDF (301/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
INCFSZ
Increment f, skip if 0
Syntax:
[ label ] INCFSZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Status Affected: None
Encoding:
0011 11da ffff ffff
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in W. If ’d’ is 1, the result is
placed back in register ’f’ (default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Decode
Read
register ’f’
If skip:
Q3
Process
Data
Q4
Write to
destination
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q4
No
operation
Q1
No
operation
No
operation
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
No
operation
No
operation
Example:
HERE INCFSZ CNT
NZERO :
ZERO :
Before Instruction
PC
= Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC
= Address (ZERO)
If CNT ≠ 0;
PC
= Address (NZERO)
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ] INFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected: None
Encoding:
0100 10da ffff ffff
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in W. If 'd' is 1, the result is
placed back in register 'f' (default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead, making it a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Decode
Read
register ’f’
If skip:
Q3
Process
Data
Q4
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
operation
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG
Before Instruction
PC
= Address (HERE)
After Instruction
REG = REG + 1
If REG ≠ 0;
PC
= Address (NZERO)
If REG = 0;
PC
= Address (ZERO)
 2002 Microchip Technology Inc.
DS41159B-page 299