PIC18F258 Datasheet, PDF (192/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
RX (pin)
Rcv shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
START
bit bit0 bit1
START
bit7/8 STOP bit bit0
bit
Word 1
RCREG
START
bit7/8 STOP bit
bit
Word 2
RCREG
bit7/8 STOP
bit
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
PSPIF
ADIF
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS41159B-page 190
Preliminary
 2002 Microchip Technology Inc.