PIC18F258 Datasheet, PDF (265/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
REGISTER 24-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7
bit 0
bit 7-4
bit 3-1
Unimplemented: Read as ‘0’
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
Note: The Watchdog Timer postscale select bits configuration used in the PIC18FXXX
devices has changed from the configuration used in the PIC18CXXX devices.
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 24-4: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h)
R/P-1
U-0
DEBUG
—
bit 7
U-0
U-0
U-0
R/P-1
U-0
R/P-1
—
—
—
LVP
—
STVREN
bit 0
bit 7
bit 6-3
bit 2
bit 1
bit 0
DEBUG: Background Debugger Enable bit
1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
Unimplemented: Read as ‘0’
LVP: Low Voltage ICSP Enable bit
1 = Low Voltage ICSP enabled
0 = Low Voltage ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause RESET
0 = Stack Full/Underflow will not cause RESET
Legend:
R = Readable bit
C = Clearable bit
- n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 263