PIC18F258 Datasheet, PDF (95/384 Pages) Microchip Technology – High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN

PIC18FXX8
9.0 I/O PORTS
Depending on the device selected, there are up to five
general purpose I/O ports available on PIC18FXX8
devices. Some pins of the I/O ports are multiplexed
with an alternate function from the peripheral features
on the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
Each port has three registers for its operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch).
The data latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
9.1 PORTA, TRISA and LATA
Registers
PORTA is a 7-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= ‘1’) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISA bit (= ‘0’)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
On a Power-on Reset, these pins are configured as
inputs and read as '0'.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
Read-modify-write operations on the LATA register,
reads and writes the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The
RA4/T0CKI pin is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input
levels and full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1). On a Power-on Reset, these pins are
configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
EXAMPLE 9-1: INITIALIZING PORTA
CLRF PORTA ; Initialize PORTA by
; clearing output data latches
CLRF LATA ; Alternate method to clear
; output data latches
MOVLW 07h ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0xCF ; Value used to initialize
; data direction
MOVWF TRISA ; Set RA3:RA0 as inputs,
; RA5:RA4 as outputs
FIGURE 9-1:
RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
RD LATA
Data Bus
WR LATA or
WR PORTA
D
Q
CK Q
Data Latch
D
Q
WR TRISA
Analog
Input Mode
CK Q
TRIS Latch
VDD
P
N
I/O pin⁽¹⁾
VSS
RD TRISA
Q
D
TTL
Input
Buffer
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 9-2:
RA4/T0CKI PIN BLOCK
DIAGRAM
RD LATA
Data Bus
WR LATA or
WR PORTA
D
Q
CK Q
Data Latch
D
Q
WR TRISA
CK Q
TRIS Latch
RD TRISA
N
VSS
TTL
Input
Buffer
RD PORTA
TMR0 Clock Input
Q
D
EN
Note 1: I/O pin has diode protection to VSS only.
I/O pin⁽¹⁾
Schmitt
Trigger
Input
Buffer
 2002 Microchip Technology Inc.
Preliminary
DS41159B-page 93